1. Field of the Invention
The invention relates to semiconductor integrated circuits with multilevel interconnections, and more particularly to semiconductor multilevel interconnections with improved multilevel interconnections of five or more wiring layers.
2. Description of the Related Art
A scaling down of the semiconductor integrated circuits may allow a reduction of resistance in the ON-state of MOS field effect transistors of semiconductor integrated circuits, to thereby achieve a high speed performance of the gate circuits of the semiconductor integrated circuits. 0n the other hand, the scaling down of the semiconductor integrated circuits also requires a reduction of a width of each of the interconnections connecting the gate circuits of the semiconductor integrated circuits. The reduction of the width of the interconnections results in an increase in the resistance of the interconnection. The scaling down of the semiconductor integrated circuits requires an increase in the number of the gate circuits of the semiconductor integrated circuits. The increase in the number of gate circuits results in a complicated layout of the interconnections connecting the gate circuits, thereby making it difficult to shorten the length of each of the interconnections. As a result, the RC time constant is increased, thereby a delay time of each of the interconnections of the semiconductor integrated circuits is significantly increased.
As disclosed in U.S. Pat. No. 5,060,045, semiconductor integrated circuits having multilevel interconnections consisting of a plurality of interconnection layers face the problems described below. A reduction of the pitch between the interconnections due to the scaling down of the semiconductor integrated circuits may result in an increase in the interconnection delay time. Particularly, the interconnection time delay is greatest, when the interconnection has a large length, as illustrated in FIG. 1. In large length and small pitch interconnections, the time delay of the interconnection is greater than a time delay of the gate circuits. When seeking to suppress the time delay of the interconnection, reducing the interconnection pitch to 1 micrometer or less results in a lowering of the speed performance inversely proportional to the scaling down and a lowering of the density of the integration of the semiconductor integrated circuits.
To solve the above problems, it was proposed to vary the pitch of the interconnections for each of the interconnection layers disclosed in Japanese Laid-open Patent Appln. No. 60-34039. The semiconductor integrated circuits disclosed therein include a plurality of interconnection layers, for example, first to fourth interconnection layers. The first interconnection layer is the first layer from the bottom layer. The second interconnection layer is the second layer from the bottom, and overlies the first interconnection layer. The third interconnection layer overlies the second interconnection layer. The fourth interconnection layer overlies the third interconnection layer. As illustrated in FIG. 2, the first interconnection layer includes a plurality of first interconnections 301 aligned in parallel in a first direction, so as to have a first pitch "a" relative to adjacent interconnections. The second interconnection layer includes a plurality of second interconnections 302 aligned in parallel in a second direction vertical to the first direction, so as to have a second pitch "b" relative to adjacent interconnections. The third interconnection layer includes a plurality of third interconnections 303 aligned in parallel to the first direction, so as to have a pitch equal to two times the first pitch, relative to adjacent interconnections. The fourth interconnection layer includes a plurality of fourth interconnections 304 aligned in parallel to the second direction, so as to have a pitch equal to two times the pitch of the second pitch, relative to adjacent interconnections. The above interconnection structure permits the top interconnections having the large pitches to have larger lengths and large widths, thereby allowing the resistance of the top interconnection to be small. The top interconnections 303 and 304 have priorities in use over the bottom interconnections 301 and 302 so as to reduce the time delay of the top interconnections, wherein the top interconnections have larger lengths than the lengths of the bottom interconnections.
The above interconnection structure, however, has a problem related to the difficulty in improving the density of the circuit integration due to the limitation of increasing the number of the top interconnections having the large pitches.
Another way to solve the above problem is disclosed in Japanese Laid-open Patent Appln. No. 63-132448, in which an automatic layout design method was proposed. A width of the interconnection is varied in the automatic layout process to comply with the requirement of allowed delay times of the interconnections. Still another way to solve the above problem is disclosed in Japanese Patent Appln. No. 1-43800, wherein the interconnection pitch of the macrocells is 2.5 micrometers or more. As illustrated in FIG. 3, an interconnection connecting two cells having a small distance is designed to have a small width, while an interconnection connecting two cells having a large distance is designed to have a large width.
The above and still other interconnection structures requires varying the interconnection pitch according to the required various properties of the interconnections, thereby resulting in keeping the alignment rules of the interconnections normally required by the gate arrays and the standard cells. If these interconnection structures are used, the required algorithm for the computer-aided design layout between the gate circuits and the cells is considerably complicated, thereby resulting both in difficulty in ensuring high density of integration of the interconnections and resulting in a large amount of time necessary for the calculations of the computer-aided design layout.
It is therefore necessary to develop multilevel interconnection structures that are able to prevent an increase in the time delay of the interconnections and to allow an improvement in the integration density of the interconnections as well as to allow for an automatic layout design.